Doe Hyun Yoon is a research staff member at IBM Thomas J. Watson Research center. He was a post doctoral researcher at HP Labs, received his Ph. D. degree in electrical and computer engineering at the University of Texas at Austin, studied at Stanford University and Yonsei University, and was a research engineer at LG Electronics. His Ph.D research advisor was professor Mattan Erez. His research includes a broad range of computer architecture, focusing on memory systems.

Education

  • The University of Texas at Austin, Austin, Texas, USA [Sep. 2007 - May 2011]

    • Ph. D. in Electrical and Computer Engineering
    Dissertation: Flexible and Efficient Reliability in Memory Systems
    Advisor: Professor Mattan Erez

  • Stanford University, Stanford, California, USA [Sep. 2005 - Jun. 2007]

    • Master of Science in Electrical Engineering

  • Yonsei University, Seoul, Korea [Mar. 1998 - Sep. 2000]

    • Master of Science in Electrical and Computer Engineering
    Dissertation: A study on an efficient test for SRAM using dynamic power supply current
    Advisor: Professor Sungho Kang

  • Yonsei University, Seoul, Korea [Mar. 1994 - Feb. 1998]

    • Bachelor of Science in Electrical Engineering

Work and Research Experience

  • IBM Thomas J. Watson research center, Yorktown Heights, NY, USA

    • Research staff member [Jun. 2013 - Present]
    Manager: Fabrizio Petrini
    Research on high-performance systems

  • Intelligent Infrastructure Lab (IIL), HP Labs, Palo Alto, CA, USA

    • Post-doctoral researcher [Jul. 2011 - Apr. 2013]
    Managers: Dejan Milojicic, Partha Ranganathan, and Robert Schreiber
    NVRAM architecture for exa-scale systems

  • LPH research group, The University of Texas at Austin, Austin, Texas, USA

    • Research assistance [Jan. 2008 - May 2011]
    Reliability issues in memory systems: Two-tiered error protection for caches and main memory, virtualizing redundant information within the memory hierarchy, flexible error tolerance levels, and adaptive granularity memory systems

  • Exa-scale Computing Lab., HP Labs, Palo Alto, California, USA

    • Research associate (Summer intern) [May 2010 - Aug. 2010]
    Mentors: Naveen Muralimanohar, Jichuan Chang, Partha Ranganathan, and Norm Jouppi
    NVRAM Reliability: Device- and system-level reliability of emerging non-volatile memory technologies

  • ECE, The University of Texas at Austin, Austin, Texas, USA

    • Independent study with professor Derek Chiou [Sep. 2007 - Jun. 2008]
    Multi-processor prefetching: Exposing prefetch operations to coherence protocols to avoid prematured ownership prefetching in multi-processor systems

  • CCRMA, Stanford University, Stanford, California, USA

    • Independent study with professor Marina Bosi [Apr. 2007 - Jun. 2007]
    Arithmetic coding in audio codecs: Applying an advanced entropy coding method - recently adopted in image/video codecs, but not in audio codecs - to AAC.

  • Design verification team, MIPS technologies, inc., Mountain View, California, USA

    • Engineering intern [Jun. 2006 - Sep. 2006]
    Verification coverage analysis tool for on-chip bus transactions

  • Digital Media research lab., LG Electronics, Seoul, Korea

    • Senior research engineer [Mar. 2004 - Sep. 2005]
    SVC standard: Research and standard activity in the MPEG/JVT meeting for the scalable extension of H.264/AVC
    DSP system programming for TI OMAP processor: Integrating multimedia codecs, managing real-time tasks, and inter-processor communication between ARM9 and DSP in LGE's multimedia platform for 3G cell phone products

    Junior research engineer [Jan. 2000 - Feb. 2004]
    Video codec development: H.263/H.263+/MPEG-4 Simple profile on TI C55x DSP, including video coding algorithms, C and assembly level optimization, stream style frame buffer management using DMA, error resilience/concealment, QoS improvement, and Inter-Operability Testing (IOT).
    Audio codec development: MP3 audio codec on TI C54x/C55x DSPs including floating point to fixed point conversion and low-level optimization

  • Computer systems lab., Yonsei University, Seoul, Korea

    • Research assistant [Jan. 1998 - Dec. 1999]
    SRAM testing and test pattern compaction

Teaching Experience

  • Teaching assistant - EE360N computer architecture, The University of Texas at Austin

    • Fall 2008 (class by professor Derek Chiou) and Spring 2008 (class by professor Mattan Erez)

  • Teaching assistant - EE265 signal processing lab., Stanford University

    • Spring 2007 (class by professor Teresa Meng)
    Fall 2006 and Winter 2007, class preparation: lab guidelines and solutions with Caleb Kemere and professor Teresa Meng

  • Teaching assistant - Digital logic lab., Yonsei University

    • Spring 1998, Fall 1998, and Fall 1999

Professional Activities

  • Program committee (PC) member: IPDPS 2012, SBAC-PAD 2013
  • Review committee member: SELSE 2013
  • External reviewers: Computer architecture letters (2011, 2012),
    IEEE Transcations on Computers (2010, 2011, 2012), IEEE MICRO (2011),
    ICCD 2010, HPCA 2012, ISPASS 2012, MICRO 2012, HPCA 2013

Archiecture conference schedule