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Cell BroadBand Engine

We will be studying the Cell Broadband Engine. The architecture for Cell is done by IBM. It is a non-conventional multicore architecture designed for high performance and throughput as it is used in demanding applications like games, graphics, multimedia that require realtime support. To get high performance from our processor we have to redesign our hardware and architecture as there are certain factors that limit us. The limiting factors are discussed below. To overcome these limitations paradigm shift has to be made from conventional single-core architectures to multicore architectures.

There is a need to address the demands of complex applications which have different characteristics.

  • Parallelism
  • Locality
  • Real-time
  • Limiting Factors
    • Power Wall
    • Memory Wall
    • Frequency Wall

Power Wall:

  • In order to boost performance pipeline depths have to be increased resulting in high power consumption.
  • Active Power results from switching the transistor nodes.
  • Passive Power results from leakage in transistors. As transistors get closer active power goes down but leakage does not. Passive power may become greater than active power. Thus as devices are scaled down we could potentially push up the frequency but we don’t do it which results in slower devices that do not leak as much. Thus a tradeoff has to be made between power and performance.

Attacking the Power Wall

  • Cell BE attacks the Power Wall by using a heterogenous multicore architecture.
    • Cores are specialized for their tasks making them simpler.
      • 1 Power Processing Element(PPE) for control tasks.
      • 8 Synergistic Processing Elements(SPE) for calculation and data processing.
      • Simpler cores use less power so we can have more cores per chip.
      • In order processing reduces the size of the “Instruction Window”, complexity of cores and number of transistors per core.

Memory Wall:

  • People put lots of caches assuming all memory is ideal but the user application has to be tuned to utilize the underlying cache architecture.
  • In order to hide latency extensive hardware prefetching is done which requires speculation and results in bandwidth wastage. We are paying for higher bandwidth by putting more pins on the chip.
  • Traditional Multi Core and SMP systems share the bandwidth of system memory among multiple cores thereby limiting system performance.

Attacking the Memory Wall

  • The Cell/B.E. processor attacks the memory wall using a three tier memory hierarchy.
    • System memory
    • Local Store(256 KB of private dedicated memory per SPE)
    • 128 registers per SPE
  • DMA is used to move data between system memory and local stores.
    • The PPE’s and SPE’s each have their own DMA engines.
    • A DMA engine can operate independently of PPE and SPE’s thereby freeing them to do other work.
    • By using multi buffering the latency of moving data between system memory and local memory can be partially or completely hidden.

Frequency Wall:

  • There are diminishing returns on increasing the frequency, as fallouts are plenty.
  • Increasing the frequency typically requires deeper pipelines resulting in more power. For e.g. the Intel P4 had a deep pipeline, approximately 40 stages deep.
  • Increasing the depth of the pipeline results in more resource conflicts in the instruction stream resulting in pipeline stalls.

Attacking the Frequency Wall

  • The Cell/B.E. Processor attacks the the frequency wall by using large register files and software controlled branching.
    • Having many registers reduces resource conflicts within the instruction stream.
    • Software controlled branching reduces the need for expensive branch prediction hardware.
    • Allows for deeper pipelines, which leads to higher frequencies.

Cell Overview

  • Cell is flexible 64 bit multicore architecture(contains nine processing cores).
  • Cell is a throughput oriented broadband architecture.
    • SPE is RISC Architecture with SIMD Organization and local store.
  • Cell provides Multi OS Support including RTOS/Non RTOS thus combining real time and non real time worlds. Real time support requires finishing a job by specified deadline.
    • Real time support requires overprovisioning things.
    • Requires hardware prefetching to predict performance which requires caches to be “warmed up”.
  • Cell is a security enabled dynamic architecture.
    • SPE’s are dynamically reconfigurable as secure processors.
  • Cell provides over 4GHZ of performance (shipping at 3.2GHz)
    • Peak Performance > 256 GFlops
    • Area 221mm^2
    • Technology 90nm SOI
  • Cell has regular replicated design of 8 SPE’s and 1PPE
    • 1 PPE Core(Power Processing Element) for control tasks
    • Coherent Load/Store with 32KB I&D L1 and 512 KB L2
    • 64 bit Power architecture with VMX
    • Cell has a modified power core with no out of order exceution engine. In order pipelining is done for processing element. In order to have Out of Order exceution we do simultaneous multithreading in hardware by switching to another thread.

SPE

  • Each of the SPE’s is a fully functional core with no redundancy.
  • SPE’s have no scalar instructions only 128 bit SIMD instructions.
  • SPE’s have a large register file(128 registers).Thus register renaming can be done to manage state explicitly in software.
  • Each SPE has a load store unit(LSU) that cannot manage offchip memory. LSU can only access local store.
  • Each SPE has a memory flow controller that is used to run DMA commands. DMA commands are used to tell the DMA engine to bring in a block of memory from system memory to be put in the local store. This mechanism ensures there are no unpredictable memory latencies.
  • SPE’s don’t have sufficient control hardware to do branching. There is no way to do arbitrary load and stores which means porting Operating Systems on SPE’s is difficult.
  • SPE’s are deeply pipelined.
  • Local Store provides all the data to SPE. Everything is shared in the local store.
  • DMA operation in SPE’s is always done in granularity of 128 bytes.

Element Interconnect Bus(EIB)

  • EIB has a ring design.
    • Thus we can take two cells and connect them back to back which is not possible in a crossbar design.
    • Thus EIB allows the design to be scaled up to a larger size.
  • EIB provides 96 B/cycle peak bandwidth.

Flexible Programmable I/O Interface

  • In a conventional processor I/O is done through PCI-X interface which is a performance limiter.
  • This limitation is overcome in the Cell architecture as each SPE has its own 32 bit mailbox. As mailbox gets full, the controller specifies that a new message has arrived.
  • Cell’s I/O Interface has two configurable interfaces.
    • Configurable number of bytes.
    • Coherent or I/O protection.
  • I/O Interface allows for multiple system configurations.

Cell Merrimac Comparison

  • Local store is partitioned across processing elements in cell and across clusters in Merrimac.
  • Both Cell and Merrimac are based on 90nm design.
  • Cell has 32 bit ALU’s whereas Merrimac has 64 bit ALU’s.
  • Cell has 2MB of RAM in SPE’s local store, 1 MB in Merrimac.
  • Cell has ring design for Bus whereas Merrimac has a crossbar design.
  • In Cell we do all operations in 4 word granularity(which makes it more difficult for the programmers) whereas in Merrimac we do everything in word granularity.
  • Cell has 7 4-wide floating point instructions in flight at any given time whereas Merrimac has around 24 single word instructions (both per PE).
  • Both Merrimac and cell use static scheduling.
  • Merrimac has a sophisticated memory controller whereas in Cell the software has to ensure memory operations are arranged in an appropriate way.
  • In Cell each of SPE’s run its own instructions in a MIMD fashion whereas the clusters in Merrimac use SIMD.
  • Cell can run a task on each of the SPE’s in addition to Asynchronous DMA Operation. Thus multiple kernel invocations are possible in Cell.
    • DMA must be controlled by the SPE kernel.
  • Merrimac can launch only one kernel and 2 DMA operations at a time.
    • DMA’s are fully independent of the kernel unlike Cell.

ashekhar?