Lecture 20: Programming the Cell BE (The concept in slides is not copied into this note)
Cell is more difficult for programming. Parallelism in Cell PPE The PPE is a in-order PowerPC processor, has two-way SMT. It is normally used for the control code, and must make sure all the SPU cooperate together.
SPE The eight SPE(Synergistic Processing Elements) are for all the computing task, each of them has four multiply-add units, the frequency is 3.2Ghz. In the PS3, there are 2 SPE can not be touch, only the other 6 could be programmed.
The SPU can only access the local store, can not read the off-chip memory. In order to get something from IO/GPU/others, the only way is to do DMA command. (eg. “give me a block form memory……, or read a collection”). Since the program in the SPU need to read data from the interconnect network, it need to make sure the DMA is done before the computing.
Most compute tasks go to the 8 SPEs, each of them support 4 vectors, no scalar computation supported. On the other hand, each is like a two-way superscalar, odd pipeline is for branch, even one is for computation. So, the DLP is supported by the 4-vectors, the ILP is supported by the 2-ways execution.
The asynchronous in the DMA, is like the software pipeline, hiding latency from the main memory, which is critical for hiding latency.
Locality The L1/L2 cache in PPE SPE: register, local storage. Each register is in 4word.
Communication and Synchronization in Cell Element Interconnect Bus (EIB) consists of several rings connect all the SPE/PPE, it is a logical bus. All the communications happen on the EIB.
PPE L2 cache coherence supported. SPE local store does not have cohere nce. We can map SPE storage to global address, each SPE must do the synchronization explicitly. For synchronization, mail box or DMA. DMA only get data from the main memory, not put data into L2 cache.
Software Challenges SPE must be scheduled by software. PPE only do top level control and IO, usually quite busy. SPE is for compute, using different ISA with PPC architecture The synchronization is tricky. PPE→SPE use mailbox, The local store can be mapped to the main memory name space, the EIB can handle it. SPE, everything must be from DMA, can not go anywhere, need explicitly manage everything, There are no memory protection in Local store, the stack, heap, may be overlaid by the data. The DMA alignment is the most painful, getting continuous memory is good, but if not alignment, loss performance. In SPE, the DMA is asynchronous; memory barrier must be inserted, to make sure the DMA is done. In each DMA command, the main parameters are: stride into memory, total size and the star address. DMA can be chained and only need synchronization once. SPE only support Vector Local sore is only the SRAM in SPE Stack may eat the data and inst Inst fetch has lower priority than DMA, the programmer have to force inst-fetch.
Sequioa
Multiple hierarchy memory Portability: only compiled once, for all the machines.
The largest challenge is the communication the parallelism is there, it easy the locality/communication is the hard part. Locality/bandwidth
To localize, just move data to lower lever, to hide the latency, can do software pipeline. It is the bulk/streaming style.
Computing bandwidth is much bigger than the memory bandwidth. The key is maximizing the use of one of the resource. The programmer must know ahead of time, what the code need to prefetch to the local level. It means the programmers have to know the working set ahead. Streaming could be in reg/code, or message passing or cluster …., it is out of the core algorithms. they need explicitly communication, are in same style, but different implementation.
The programmer need to handle all level of locality, otherwise will lose performance. If the programmers want to get efficient code, they always has to take low-lever hierarchy into account.
Locality in programming languages Past: focus on communication, not in vertical Now: manage vertically (L1, L2 … memory …) The difference (1)The old languages, such as CUDA, GPU, Brook, CG(Bill Mark is one of the main developer) are all for only one hardware, not portable. (2) The old languages only has two levels, they have no way for more arch, such as cluster. (3) some hierarchy-aware model is not programming environment.
Sequioas: (1) may do thing in many hierarchies (2) keep the portability. (3) Does not require advanced compiler technology
Hierarchical memory in Sequoia (Dr.Erez mainly repeated the slides of this part during the class, please refer to the slides for more details) Sequoia tasks Inner Task: Not be the root, also not be the leaf, it is in the middle, and recursively call inner task itself until inner task fit into the leaf nodes. Tunable: is predefined value, can be modified by hand, or the software system may change it. Mappar{} //do here in parallel. Mapseq{} //do it in sequential. In the future, the best value of tunable will be fined the compiler, but now, the programmer need to do it. Working set: defined in the interface of the task (In/Out/Inout), “In” will be copied into leaf nodes before execution; output will be copied to the host after execution. Copying name space of A from L2 to L1, it is kind of bulk communication, the leaf nodes do not need any more data from up level until finish. Before execution, data transfers from caller to callee; after finish execution, the data is from callee to the caller. No communication among the nodes in the same layer is allowed in Sequoia model.
Synchronization Each time of Mappar used, the control will not return until all the task finish Each time of Mapseq used, the control will return when each task finish.
