General
Cell is the only heterogeneous multicore currently in mass production. One of it’s purposes is real-time software. Real-time is not about being fast about about providing the result in the specified time limits. In addition cell is attempting to be efficient. Efficiency has many faces, performance per power (watt), performance per memory B/W and so on. Due to the way cell is built, running a non parallel / locality abusing application on it won’t be a good idea and is not the purpose.
Cell targets
Cell path finding was during be early 2000. Existing limitation at that time were:
- power wall - limitation by watts we can cool down
- memory wall - due to the gap between cpu and memory speed the performance of cpu starts being limited by the memory access latency
- frequency wall - increasing frequency requires deeper pipelines and becomes less efficient. Therefore it needs uarch compensation.
Power
There are several components to VLSI power:
- active power - power dissipated due to switching
- leakage power - even when there is no switching activity, due to physics, once transistors became small as today (2000) they dissipate power just due to “existence”.
Observing the impact of both over time, leakage power had grown rapidly. One of the reasons is that for a long time it was neglected and wasn’t been taken into account. But not anymore. Power optimizations should be cross design and not only for active power. Just the existence of each transistor even without being switched has a significant power impact in modern VLSI.
Memory
Latency is decreasing much slowly than B/W is increasing. Therefore, the way to avoid the negative impact of the cpu/memory gap is to move towards B/W (throughput) oriented architecture which doesn’t care about latencies.
Efficiency
Putting together Moore and Gelsinger’s predictions it turns out that the actual efficiency of cpus is decreasing by rate of x1/1.4 in each new generation using the existing paradigm. It required a novel approach. This actually was a behavior for a long time, the cpu efficiency growth which was approximately linear with rate of 58% was bellow the rate of VLSI improvement which had a rate of 78% approximately. However, until recently this gap was not yet large enough to encourage a totally new approach.
Performance
Separate units for control and computation are used to gain more efficient performance. Memory “shopping list” (gather/scatter) shift from latency sensitive towards B/W oriented paradigm. Performance is achieved by giving more control to software, simplifying the computation pipeline making it no longer latency limited.
Frequency
Cell cycle time is 11FO4 where FO4 stands for the delay of a single gate to drive 4 gates and is been known as a well scalable with a process metric. This cycle time is relatively short which implies high frequency and a deep pipeline.
Cell as a scalable SoC
Due to increased production prices by several order of magnitude, the intention was to make cell more programmable so it will be an array of a simple programmable, yet efficient computational units in SoC manner. It didn’t really work out. Cell didn’t work for graphics, in PS3 a dedicated NVIDIA GPU is used for graphics. A few of the reasons for the failure in graphics area are: lack of graphics dedicated hardware, interconnection architecture and bigger sizes of computational units (which doesn’t allow having many of them as in GPU).
Cell vs GPGPU
Implementing a protein folding application on cell is straight forward and gives a performance boost right away. Implementing the same application on GPGPU is doable but required rethink of the problem and conceptional changes to the algorithm (numeric techniques).
Cell internal structures
- SPE - small core unit
- SXU - grouping of execution functional units and registers
- LS - local store
- SMF - memory flow controller for interfacing the SPE with memory
- SPU=SXU+LS
- SPE=SPU+SMF
- PPE - redesigned PowerPC core processor. Inorder with 2 SMT. Had to be redesigned to meet cell requirements as frequency and communication interfaces.
All the cores are connected among them and to the memory/io controllers with a ring consisting 2 fully pipelined(buffered) rings in each direction.
SPE
Each SPE operates 4-wide vectors of 32-bits and perform 4 mul-adds per cycle single precision. However, not designed initially for double-precision which makes it less efficient (PowerXCell-8i is a 65nm version with full DP support).
SPE can execute 2 instructions per cycle but only one of them can be computational and the other a control instruction. It has no branch predictor, assuming branches are always taken which requires more support from software (compiler) to avoid performance loss. All operations are done on 4 wide vectors. No way to operate on scalars. The whole internal pipeline control is done by software which knows all the expected latencies ahead of time.
The ATO unit is a dedicated SPE’s sub unit handling locks.
LS
LS is a 256K in 4 banks of SRAM used data/instructions with no overflow protection (each one can overwrite the other). Load/stores, DMA in/out transactions and instruction fetches, all use LS. LS has only single port. To reduce contentions as much as possible, each operation is done in bulks. DMA accesses are for 128B granularity. Instruction reads in 64B granularity. This way more available slots for memory instructions (load/store) are left.
While most of the LS accesses are known to software ahead of time along with their expected response times, DMA are not known which might lead to complicated cases as instruction fetch starvation on some circumstances. There are dedicated instructions to handle these cases.
Interconnect
On the ring, each hop takes 2 cycles (operates in half frequency), the bandwidth for core-to-core communication is 96B per cycle. However, only 16B per cycle towards the memory controller and 32B per cycle towards the IO. IO is used for efficient communication with the GPU. In other cell usages IO can be used to connect back to back 2 cell processors for example, emulating a cell processor with 16 SPEs. However, the cross (cpus) communication will be B/W limited to the B/W of IO access - 32B per cycle. * - the second PPE in this configuration will be inactive.
The bottom line
Cell is a B/W oriented architecture making use of exposed parallelism and locality and meets the initial targets.
