CPU Locality and VLSI Interconnect
This lecture deals with two separate topics: finish locality mechanisms in CPU and move to properties of interconnect in modern VLSI.
CPU Locality
See slides
VLSI Interconnect
Points from assignment
- Medium-range wires have higher bandwidth density, but in the graph they were shown for a smaller block.
- Wires were optimized for minimum delay-power.
- Typically try to minimize repeaters while meeting delay or BW to reduce area overhead.
Definitions
- FO4
- Delay of inverter driving a load equal to 4 inverters identical to itself. Delay expressed as FO4s remains constant across technologies (from ~2 micron to 65nm).
- FO1
- Like FO4 but fanout of 1. Usually \sim {1 \over 3}FO4
- \mathbf{\chi}
- minimal M1 pitch. Distances remain constant across technologies if expressed in this unit.
- \lambda
- used to be technology independent parameter, but not as much now that circuits are wire-limited.
- Generally \chi = 4 \lambda.
Wire Properties
- Delay, BW (area), and power/Energy, but first R, C, L, l, and V
Physical properties
- Length (dimensions)
- can scale with technology (local wires) (\chi shrinks).
- but global chip-level lengths are constant or slightly growing (chip dimensions grow in terms of \chi.
- Aside, why don’t we make gigantic chips?
- number of metal layers keeps going up.
- in general, min wire thickness and pitch roughly 1.5X - 2X per step for local → intermediate → global wires.
- but wire height also grows with higher layers (especially top-level), which affects resistance (later).f
- Supply voltage
- Used to scale down with technology (same ratio as length).
- Not anymore though, voltage has stabilized ~1V or 0.9V.
- Why? Balance of leakage and speed.\ (Vth can’t keep going down).