VLSI Interconnect

What is wire problem?

The latency of wire is not improving with respect to the latency of transistor as the technology scales down. Wire problem is that latency is not scaling up with technology. Logic is getting faster, but wires are not catching up.

Die size almost remains same over technology. Distance which can be covered in one cycle is shrinking.

Speed of wire:

Lumped-element model interconnect: Entire wire needs to swing. Delay depends on RC.

Different from transmission lines which are distributed-element circuits. Delay for transmission line depends on RLC. Transmits at speed of light.

Most of the lines “L” is very less and hence acts as lumped circuits.

Communication:

Bandwidth: Frequency of charging and discharging. I can’t send other signal until the older signal has reached other end

Bandwidth = 1/latency; (for single wire)

Scaling

Parameters

scaling factor, {$ \alpha = \frac{Min pitch_\textit{new}}{Min pitch_\textit{old}} $}; {$ \alpha$} < 1

Width - shrinks by {$\alpha$} Length - shrinks by {$\alpha$} (for local wires) Pitch - shrinks by {$\alpha$}


Equal signs below generally represent approximate and proportional, rather than true equality.


Resistance

Resistance, {$ R = \frac{length}{height * width} * \rho $}

Capacitance

Capacitance, {$ C = \frac{K * W * L}{t} $}

Total Capacitance, {$ C = K * (\frac{W}{t_{ox}}+\frac{h}{t_p}) $}

K - Dielectric constant

{$ t_ox - Oxide thickness $}

{$ t_p - Thickness with respect to ground plane $}

Latency

What we really care is RC

{$ RC = \rho * K * (\frac{W}{t_{ox}}+\frac{h}{t_p}) * (\frac{1}{W*h}) $}

RC: almost constant. Therefore no loss and no gain.

Different way of analyzing:

{$ R ~ R_0 * L $}

{$ C ~ C_0 * L $}

Global wires have fixed length.

Local wires have scaled length.

Fixed/Global: {$ RC = {L_0}^2 * R_0 * C_0 $}

Scaled/Local: {$ RC = {L_0}^2 * {\alpha}^2 * R_0 * C_0 $}

So, as we scale down, if the wire scales in length (local wire) the delay stays constant, but if the wire does not scale (global wire) delay scales with {$ \frac{1}{\alpha^2} $}

So long global wires are a problem because delay goes up quadratically. What to do?

  1. By using repeaters for global wires, delay scales only with {$ \frac{1}{\alpha} $}
    • delay is now linear
    • power is high due to repeaters
    • vias cause major congestion and problems for CAD tools
  2. By taking advantage of RLC we can build on-die transmission lines
    • speed of light transmission
    • for low latency, less than a cycle delay
    • power and area problems
  3. Capacitive feed-forward low-swing
    • delay is reasonable
    • better power
    • better bandwidth per wire, but less overall wires so perhaps constant total bandwidth

Bandwidth

  • unrepeated wires, simply {$ \frac{1}{delay * density} $}
    • delay and density go down with wider wires
      • optimal exists for global mostly
  • repeated, same but per wire-segment (which does scale)
    • {$ \frac{1}{segment-delay * density} $}
    • repeated wires have increasing BW with technology
  • global wires have higher BW per wire, but fewer wires. Global bandwidth scales only by increasing the number of wires.
    • around 500 50K blocks on .18 so 10X more BW in semiglobal wires
    • another order of magnitude for local wires
  • low-swing techniques can have higher BW per wire
    • but again, fewer wires because of extra circuits, so perhaps ~constant BW.