Lecture {$\#6$} - Scaling - September 14, 2011

  • Error Density of Fabrication
    • The larger the die, the more likely a manufacturing defect is present on it.
  • Scaling
    • Define Scaling constant {$\alpha$}: ratio of new process to old process
      • {$\alpha = \alpha_{\mathrm{new}}\div\alpha_{\mathrm{old}}$} ({$< 1$})
    • Does the size of chip scale?
      • No.
      • Process technology shrinks, meaning more transistors fit in the same area, but..
      • The trend has been that the Size of chip is roughly fixed because new stuff gets added.
  • Transistors
    • {$I_{\mathrm{DS}} = \left(\frac{\mu_nC_{\mathrm{ox}}}{2}\right)\left(\frac{W}{\ell}\right)\left(V_{\mathrm{GS}}-V_{\mathrm{th}}\right)^2\left(1+\lambda\left(V_{\mathrm{DS}}-V_{\mathrm{DS,sat}}\right)\right)$}
    • {$C_{\mathrm{ox}}$} is capacitance per unit area
      • {$C_{\mathrm{ox}} = \kappa_{\mathrm{ox}}\varepsilon_0\frac{1}{t_{\mathrm{ox}}}$}
    • {$C_{\mathrm{gate}} = C_{\mathrm{ox}}W\ell$}
    • Do the sizes of transistors scale?
      • Width (of channel)? Yes, scales by {$\alpha$}
      • Length (of channel)? Yes, scales by {$\alpha$}
      • Thickness (of oxide)? Yes, scales by {$\alpha$}
    • What is the impact of scaling on transistors?
      • {$C_{\mathrm{ox}}$} scales by {$\frac{1}{\alpha}$}
      • {$C_{\mathrm{gate}}$} scales by {$\alpha$}
      • Approximating {$V_{\mathrm{GS}} = V_{\mathrm{DS}} = V$}, and {$\lambda = 0$},
        • {$I = \left(\frac{\mu_nC_{\mathrm{ox}}}{2}\right)\left(\frac{W}{\ell}\right)\left(V-V_{\mathrm{th}}\right)^2$}
        • {$I \propto C_{\mathrm{ox}}\left(\Delta V\right)^2 \propto \frac{\left(\Delta V\right)^2}{\alpha}$}
        • If {$V$} were held constant, current goes up
  • Wires
    • What is the speed (frequency) of a wire?
      • Rate in which you can repeatedly (dis)charge
    • (dis)charge latency {$\propto R_{\mathrm{wire}}C_{\mathrm{wire}}$}
    • {$R_{\mathrm{wire}}/\ell_{\mathrm{wire}} = \frac{\rho}{H_{\mathrm{wire}}W_{\mathrm{wire}}}$}
    • {$C_{\mathrm{wire}}/\ell_{\mathrm{wire}} \propto \kappa\varepsilon_0\left(\frac{W_{\mathrm{wire}}}{t_{\mathrm{ox}}}+\frac{H_{\mathrm{wire}}}{t_{\mathrm{pitch}}}\right)$}
    • {$\Rightarrow$} (dis)charge latency {$\propto \ell_{\mathrm{wire}}^2$}
    • {$\Rightarrow$} wire speed (frequency) {$\propto 1/\ell_{\mathrm{wire}}^2$}
    • How do wires scale?
      • Width scales by {$\alpha$}
      • Height scales down
      • Pitch scales down
      • Dielectric between wires ({$\kappa$})?
    • If we assume just {$\ell_{\mathrm{wire}}$} scales by {$\alpha$} (because things on chip aren’t as far apart){$\dots$}
      • {$R_{\mathrm{wire}}$} scales by {$\alpha$}
      • {$C_{\mathrm{wire}}$}
        • For the {$\frac{W_{\mathrm{wire}}}{t_{\mathrm{ox}}}$} term, {$\ell_{\mathrm{wire}}$}’s scaling cancels out {$t_{\mathrm{ox}}$}’s
        • The {$\frac{H_{\mathrm{wire}}}{t_{\mathrm{pitch}}}$} term scales by {$\alpha$}
        • Assuming {$\frac{W_{\mathrm{wire}}}{t_{\mathrm{ox}}} \gg \frac{H_{\mathrm{wire}}}{t_{\mathrm{pitch}}}$}, the net effect is that {$C_{\mathrm{wire}}$} remains {$\approx$} constant
      • {$\Rightarrow$} Wire delay scales by {$\approx \alpha$} (decreases — what we want)
    • If we also let {$W_{\mathrm{wire}}$}, and {$t_{\mathrm{pitch}}$} scale by {$\alpha\dots$}
      • {$R_{\mathrm{wire}}$} no longer scales by {$\alpha$}
        • It is now the same as before scaling (at least it’s not worse!)
      • {$C_{\mathrm{wire}}$} is no longer {$\approx$} constant
        • For the {$\frac{W_{\mathrm{wire}}}{t_{\mathrm{ox}}}$} term, all variables ({$W_{\mathrm{wire}}$}, {$t_{\mathrm{ox}}$}, and {$\ell_{\mathrm{wire}}$}) now scale by {$\alpha$}, so the net effect is that this term scales by {$\alpha$}
        • The {$\frac{H_{\mathrm{wire}}}{t_{\mathrm{pitch}}}$} term has {$t_{\mathrm{pitch}}$}’s scaling counteracting {$\ell_{\mathrm{wire}}$}’s, so that this term is now constant
        • Once again, assuming {$\frac{W_{\mathrm{wire}}}{t_{\mathrm{ox}}} \gg \frac{H_{\mathrm{wire}}}{t_{\mathrm{pitch}}}$}, the net result is that {$C_{\mathrm{wire}}$} now scales by {$\approx \alpha$}
      • {$\Rightarrow$} Wire delay scales by {$\approx \alpha$} (same as before)
    • So, what do we do with {$H_{\mathrm{wire}}$}?
      • If we let {$H_{\mathrm{wire}}$} scale by {$\alpha\dots$}
        • {$R_{\mathrm{wire}}$} would now scale by {$\frac{1}{\alpha}$} (now worse than before scaling)
        • {$C_{\mathrm{wire}}$} now scales by {$\alpha$} without having to make any assumptions
        • The scalings of {$R_{\mathrm{wire}}$} and {$C_{\mathrm{wire}}$} now cancel out
        • {$\Rightarrow$} Wire delay is the same as what it was before scaling
      • But we need wire delay to be getting better{$\dots$}
      • So we don’t scale {$H_{\mathrm{wire}}$} scale by {$\alpha$}. Instead we scale it by some {$\beta$} such that {$\alpha < \beta < 1$}
        • This means that in terms of {$W_{\mathrm{wire}}$}, {$H_{\mathrm{wire}}$} is increasing with each new process technology.
        • Try to control {$\kappa$} to make up for the difference
          • Low between wires
          • High in the gate
          • ITRS (Intl. Tech. Roadmap for Semiconductors) projects that {$\kappa$} improves every three years
    • Bottom line is that wire delay is not scaling by {$\alpha$}, which means that wires are slowly decreasing in performance relative to the rest of the chip
  • Power
    • What is the power to switch a transistor?
      • {$P=C_{\mathrm{gate}}fV^2$}
        • {$C_{\mathrm{gate}}$} scales by {$\alpha$}
        • If we assume {$f$} scales by {$\frac{1}{\alpha}$}
        • then the power per transistor remains constant
    • What about leakage?
      • Adds {$I_0V$} to power
    • But transistor sizes scaled in both dimensions{$\dots$}
      • {$\Rightarrow$} Power per area {$\propto \frac{1}{\alpha^2}$}
      • With die size {$\approx$} constant, that means total power would go up {$\propto \frac{1}{\alpha^2}$}
    • Solution? Lower the voltage.
      • But at a lower voltage, transistors don’t switch as fast
      • {$\Rightarrow$} scaling {$f$} and scaling {$V$} are mutually exclusive
    • Efficiency
      • Performance per Power
        • {$\propto \frac{A\cdot f}{A\cdot P} = \frac{f}{P} = \frac{f}{CfV^2+I_0V}$}
      • If leakage is high, reducing power does not improve efficiency
      • Maximum efficiency?
        • Switching power {$=$} Leakage Power
        • {$V_{\mathrm{DD}} = V_{\mathrm{th}}$}
  • Energy
    • Energy required to switch a transistor?
      • Gate Cap. ({$+$} some second order effects
      • {$\propto \alpha$} (or maybe {$\alpha\gamma$}
    • Energy required to switch a wire?
      • Only Cap. matters
      • {$\propto \alpha$} (local wires)
      • {$\approx$} const (global wires)
        • Add more (higher) layers of global wires to keep layers that have the old process’ wire performance
  • Other methods of improving global wires
    • Make {$W_{\mathrm{wire}}$} larger
    • Make them behave as transmission wires (delay {$\propto RLC$})
      • Requires additional Tx and Rx circuits
    • Put capacitors in series with repeaters (differential signaling)
      • Drives {$C$} down on global wires
      • Also requires additional Tx and Rx circuits
      • Low (voltage) swing requirements let you not hurt power so much.