7163324

Summary

Jaeyoung Park, Tianhao Zheng, Mattan Erez, and Michael Orshansky. Variation-Tolerant Write Completion Circuit for Variable-Energy Write STT-RAM Architecture. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(4):1351–1360, April, 2016. #7163324Bib

Bibtex entry

@ARTICLE { 7163324,
    AUTHOR = { Jaeyoung Park and Tianhao Zheng and Mattan Erez and Michael Orshansky },
    JOURNAL = { IEEE Transactions on Very Large Scale Integration (VLSI) Systems },
    TITLE = { Variation-Tolerant Write Completion Circuit for Variable-Energy Write STT-RAM Architecture },
    YEAR = { 2016 },
    VOLUME = { 24 },
    NUMBER = { 4 },
    PAGES = { 1351-−1360 },
    DOI = { 10.1109/TVLSI.2015.2449739 },
    ISSN = { 1063–8210 },
    MONTH = { April },
    MYCAT = { journal },
}