Virtualized and Flexible ECC for Main Memory.

Problem

  • DRAM faults/error tolerance (reliability / resilience)
    • Sources of a DRAM error
      • Soft errors (high energy particle hits the chip and flips the data of a bit cell) (shielding with a lead in the package does not help because lead itself is radio-active)
      • DRAM cell leakage (weak bit cell due to the process variation may lose the data)
      • Physical failures: pin error (most common) / manufacturing failures (dust particles)
      • Aging (depends on temperature and voltage strain)
    • Chipkill
      • In the case of an entire chip failure, use the redundancies of other chips in the module to continue

ECC

  • Error Checking and Correcting (original) / Error Correcting Code (nowadays)
    • How chipkill works
      • Each memory chip generates multiple-bit → This multi-bit is treated as a symbol and used for detecting and correcting errors → Even though there are multiple errors in a symbol, it doesn’t matter so long as the errors belong to a single symbol.
      • DRAM data transfer occurs in a burst of 4 or 8.

Trade-offs

  • Error model
    • How many wrong bits detected / corrected (how strong is the protection)
    • How many wrong chips detected / corrected (how strong is the protection)
    • How many dead chips detected / corrected (how strong is the protection)
    • Rate of incorrect data potentially corrupting execution
    • Error types
      • SDC (Silent Data Corrupt)
      • Failure
      • → Depending on the usage model, either or both can be severe.
      • (SDC is critical for financial applications whereas negligible for graphic applications)
    • Data
      • Differs in impact on user if error / vulnerability / importance

Cost

  • Sources of memory costs
    • # of components
    • Cost of parts (commodity / dedicated)
    • Capacity efficiency
    • Power
    • Complexity (transparency)
    • Performance (bandwidth / latency / execution time)

Virtualized and flexible ECC Virtualized and flexible ECC

  • Provide a flexible ECC scheme for the characteristics that you need
    • Redundancy vs. granularity of access
      • The finer the granularity, the bigger the redundancy
    • Data types
      • Some data is important, some data is vulnerable, some data is in vulnerable
  • Add a level of indirection → virtualization

Flexible ECC in GPU

  • Tesla GPU for computation provides a feature for flexible ratio of data storage / redundant info storage
  • GPGPU
    • NVIDIA makes one chip with all the features for the graphics and all the features for the computation
    • The additional cost for the computation should be cheap because the cost is amplified for the users of graphics.
    • → Use flexible virtualization for ECC
    • → Allocate the redundant information into the same chip as the data
    • → Need to read the memory twice for data and redundancy

Two-tiered ECC

  • Tier-1 for detection and tier-2 for correction
    • Reduce the overhead of reading redundancy information
    • → Because the errors are rare
    • Overhead on reads are negligible / writes have overheads of writing data and redundancy separately.

Evaluation

  • Granularity of access
    • Narrow chip data bus can increase the memory capacity of a channel
    • Wider chip data bus consumes less energy