The class scribe notes are currently restricted to students taking the course. The notes will be made public at some point, probably once the semester is over. Clickable lecture numbers have notes posted.
| Lecture | Date | Topic (notes) | Reading | Comments |
|---|
| 1 | 8/29 | Introduction and Policies | | |
| 2 | 9/5 | Users and Systems | | |
| 3 | 9/10 | GPP binary compatibility | J. Denhert et al., “The Transmeta Code Morphing™ Software: using speculation, recovery, and adaptive retranslation to address real-life challenges,” CGO’03 | |
| 4/5 | 9/12+17 | GPP source compatibility | S. Swanson et al., “WaveScalar,” MICRO 2003 | |
| 6 | 9/19 | System Simulation | D. Chiou et al., “FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators,” MICRO’07 | |
| 7 | 9/24 | Power Management | Q. Wu et al.,”A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance,” MICRO’05 | |
| 8 | 9/26 | Quiz 1 | N/A | |
| 9 | 10/1 | Defect tolerance | Background (no writeup): Y. Zorian and Z. Gizopoulos, “Design for Yield and Reliability”, IEEE Design and Test, Vol. 21, No. 3, May 2004
Research paper: W. Culbertson et al., “Defect Tolerance on the Teramac Custom Computer”, IEEE Symposium on FPGAs for Custom Computing Machines, 1997 | |
| 10 | 10/3 | Memory ECC | Yoon and Erez, “Virtualized and Flexible ECC for Main Memory”, ISCA 2010 | |
| 11 | 10/8 | Power II | C. Lefurgy et al., “Active Management of Timing Guardband to Save Energy in POWER7”, MICRO 2011 | |
| 12 | 10/10 | New Baby | N/A | |
| 13 | 10/15 | Datacenters (1) | Light reading: L. Barroso and U. Holzle, “The Case for Energy-Proportional Computing”, IEEE Computer, Dec. 2007
Research: Mars et al., “Bubble-up: Increasing utilization in modern warehouse scale computers via sensible co-locations”, MICRO 2011 | |
| 14 | 10/17 | Datacenters (2) | Lighter reading: V. Jimenez et al., “Energy-Aware Accounting and Billing in Large-Scale Computing Facilities”, IEEE Micro May/Jun 2011
Research: J. Chang et al., “A Limits Study of Benefits from Nanostore-Based Future Data-Centric System Architectures”, CF 2012 | |
| 15 | 10/22 | Datacenters (2) | Continued discussion, quite a bit of it not directly related to the paper. | |
| 16 | 10/24 | Lightweight Threads | D. E. Culler et al., “Fine-Grain Parralelism with Minimal Hardware Support: A Compiler-Controlled Threaded Abstract Machine”,ASPLOS IV, 1991.
BACKGROUND ON ID: K. R. Traub, “A Compiler for the MIT Tagged-Token Dataflow Architecture (pages 13--21 only)”, MIT Masters Thesis, 1986. | |
| 17 | 10/29 | Projects | Project discussions | |
| 18 | 10/31 | HW Active Messages | M. Noakes et al., “The J-Machine Multicomputer: An Architecural Evaluation”, ISCA 20, 1993.
PLEASE ALSO READ THIS OVERVIEW WITH PICTURES: W. J. Dally et al., “The J-Machine: A Retrospective”, 1998. | |
| 19 | 11/5 | Register Org. | S. Rixner et al., “Register organization for Media Processing” | |
| 20 | 11/7 | Cache Coherence | S. Reinhardt et al., “Tempest and Typhoon: User-Level Shared Memory” | |
| 21 | 11/12 | Supercomputing | F. Petrini et al., “The Case of the Missing Supercomputer Performance: Achieving Optimal Performance on the 8,192 Processors of ASCI Q”, SC’03 (CiteSeer) | |
| 22 | 11/14 | Quiz 2 | N/A | |
| 23 | 11/19 | Auto-parallelism | M. Bridges et al., “Revisiting the Sequential Programming Model for Multi-Core, MICRO’07 | |
| 24 | 11/21 | HW Resilience | A. Meixner and D. Sorin, “Detouring: Translating Software to Circumvent Hard Faults in Simple Cores”, DSN’08 | Other options |
| 25 | 11/26 | Stream Processing | W. Dally et al., “Merrimac: Supercomputing with Streams”, SC’03. | |
| 26 | 11/28 | Security | Background-ish paper: M. Steil, “17 Mistakes Microsoft Made in the Xbox Security System”, Chaos Communication Congress, 2005
Research paper: G. E. Suh et al., “AEGIS: Architecture for Tamper-Evident and Tamper-Resistant Processing”, ICS’03 | |
| 27 | 12/3 | Summary | N/A | |
| 28 | 12/5 | Presentations | Project Presentations | |
