Problem:
Power consumption
Current timing techniques are not efficient. Delay for different paths are not same. We design for the worst cases.
Razor: remove safe margin guarantee and recover from error.
Good chips: high frequency/low voltage (power) depends on market
High frequency v.s. low power: market need a guarantee frequency rather than “can run faster when timing margin is OK”.
Variations:
Manufactory Temperature Power supply Workload Aging
Users:
High-end workstation, server, HPC
Consider performance, power, and cost. Get as much as possible performance within certain constrains. This paper lock performance, try to reduce power.
Ways to reduce power:
Power regulator deal with long-term stuff (temperature, timing margin)
For short-term stuff, drop frequency to avoid soft failure. Use test circuits to determine delay.
Evaluation:
Less margin, less power. Minimum is 0 margin
For power, 0 margin and 50% margin are close.
There is no guarantee for “error free”, but the margin is tunable.
