Mattan Erez Courses : Fa12EE382V - Lect 6 Notes browse

FAST

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Make the simulator fast.
Make functional blocks modular, os that anyone can modify or replace those at will.
Decouple timing and functional model.
The key is how often we have to communicate between the functional and timing model.
In FAST, the timing model is always correct.
Definition
- Functional Model: one that generates instructions (ISA) (e.g. eliminates decoding if a functional model is used)

Anyone in the computer architecture research. Basically, us!
Code optimization developers
- e.g. fast simulation can let software writers do architectural level optimizations, such as optimizing for power if a certain function is consuming too much power.
OS developers can now test newer systems on future platforms.
RTL designers. Now, they can test preliminary RTL designs on FPGA for various parameters such as timing.

Feasibility to feedback to functional model from timing model.
Two different platforms (functional in software and timing in hardware).
The use of Qemu helps to enable cross platforms since it handles all x86(in case of FAST) instructions and exceptions/interrupts.
Cycles on hardware
- For example, if we want to simulate a 20 port cache, yet we only have 2 port cache, then we simulate 10 hardware cycles to emulate this 20 port cache per one functional model cycle.
Since timing model is always correct, the functional model must check if the branch prediction has been correct or not. ** Since we must make sure that the timing model is always correct, we cannot fetch instructions that are on the wrong path (not necessarily branch misprediction).
- In order to allow this, the FAST functional model checks the fetched instruction number(we assign a number to every instruction) for every single instruction.
- This is a one-way communication from timing to functional by sending the instruction number.

Ease of use is lacking as users may not be familiar with how to easily configure FPGA modules.
However, considering the amount of work done in conventional simulators (e.g. inlining and low level C code to optimize for performance), the FAST is still tolerable.

Yes, with Moore’s law, more transistors can fit in the FPGA. The number of transistors on FPGA is following the number of transistors on microprocessor chips very closely, so this trend helps the FAST research to incorporate more complex modules on FPGA.

x85 microcode compiler: This compiler basically compiles an x86 instruction to a few microcodes. Micro instructions are key to performance in x86, so this compiler is very important to achieve higher performance in FAST’s functional model.

Software and compiler writers are new users that could not use simulators in the past due to speed. Now, with FAST, those users can test their software with some architecture studies. For example, power can be studied at the software level.
Traditionally, RTL designers are not closely coupled with architects as usually RTL designers usually do fine tuning, and most of the time, it is not feasible to incorporate a significant change proposed by architects in the RTL design as the RTL design comes later in the production stage. Yet, FAST has RTL as a timing model on FPGA, so now architects and RTL designers can interact very closely in the early design stages and can make some major design changes prior to full RTL design.

FAST offers a bigger sandbox for people to play in. Due to extremely slow simulation speed, architectural simulators were not well used in other communities including OS and RTL. However, the significantly faster FAST offers a new method for those closely related to computer architecture to play a role in designing a better and more efficient future processors.