Defect Tolerance on the Teramac Custom Computer

Scribe: Song Zhang

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Problems

Chips have low yield due to manufacture defects, so need to tolerate defects, such as work around defects, to achieve lower cost.

Manufacture Defects

  • Dust on wafer
    • Cause false mask, and may cause short wires.
    • As technology scales, smaller dusts can cause manufacture defects.
    • Using clean room may help, but could not avoid this defects.
  • Etching
    • Old etching techniques may cause uneven surface.
  • Control Issue

Manufacture Variants

  • Wavelength of lights
    • Wavelength of lights and sizes of transistors are in same scale, which may cause light diffraction when printing.
    • Use liquids to shorten the wavelengths of lights may ease this problem.
  • Variances across wafer
    • As technology scales down, variances across wafer goes higher. This means, some chips may be faster than other chips.

Previous Techniques to Tolerate Variances

Focus more on inter-die variances than intra-die variances

  • Set frequency of chips to lowest frequency
    • This may cause performance degradation.
  • Sell low frequency or less functionality chips with low prices
    • Some companies may intentionally do so for low-end users.
    • This technique will increase yield ratio.

Teramac

Tolerate defects without redundancy

  • Defects Detection
    • Test good sets of gates
      • How?
        • Let gates produce pseudo-random numbers
      • Missing parts in this test:
        • NOT consider variations of gates.
        • NOT test all latches in every gate (only for configurations associated with pseudo-random number generation).
    • Test slow gates
      • Some resources may produce logically correct results but slow. This will fail some user design at expected frequency.
      • Still not good coverage, but good enough for what they did.
    • Tests
      • Tests are important
        • At least partially test the wafer before packaging, maybe through probing, because packaging is expensive.
      • Tests need to be fast, otherwise will wait long time on testing large amount of wafers.
        • Trade off between time to market and cost of test equipment. May need special circuits for testing
      • Test will be harder if taking “aging” into consideration.
    • Previous Work
      • Use spare resources to replace defective resources in a fine-grained manner.
      • NOT fine-graine for defective memory cells, whose granularity is whole row or column.
  • After Defects Detection
    • Build databases of defective resources
    • Using ample hierarchical interconnect to dynamically map applications onto “good” resources
      • Rent’s Rule
        • Power law between # of pins and # of components in a block.
        • # of external signal = {$ \sqrt{\#\ of\ logic\ gates} $} is a good approximation.
      • Hierarchical interconnection limits # of wires in high level.

Users

Users who use FPGA platform:

  • Use it as a prototype to test designs.
    • This is one of Teramac’s targets.
    • Another one is to use parallelism in FPGA to do fast gate-level simulation.
  • Use it as a replacement of low volume/expensive ASIC.

Results

  • Half price (kind of cheat it)
    • For each perfect chip, they can get one imperfect chip for free.
    • Still need good parts, because control aspects need to work.
  • Mapping software

Evaluations

  • How was Teramac evaluated?
    • Build a chip with large number of defects.
  • Matching Goal?
    • Goal is to have circuits simulation done in low cost (half-chip for free)
    • NOT included defects detection cost and interconnect redundancy cost.
    • NOT included costs of ample interconnection and routing.
      • Add lots of wires, which are expensive.
    • NOT included costs for manufacture and packaging.
      • Manufacture a multi-chip module is expensive.
        • Twice as many layers as manufacture recommended.
    • NOT included aging.
      • To be fair, aging is not a problem back then.
    • NOT proved they save money with Teramac.

Application on today

  • NOT worthy to build Teramac today, because cost of wire/transistor is too high.
    • Cannot afford so redundant interconnections.