There will be 6 regular programming labs required for all. On the first two labs only, you may work with a partner. Work on the other 4 regular labs must be your own (this means no cheating, copying, contracting, consulting, …). In this series of labs you will “build” a simple processor from the ground up, including support for interrupts and virtual memory for interaction with software. You will program in C to make the learning curve smoother and your work more productive. Yet, the labs will take time.

One critical aspect of these labs is that you are responsible for testing them well. Write good and comprehensive tests and don’t settle for the very minimal functionality tests we will provide you. When grading, we use a comprehensive array of tests, but we do not make those available to you. Writing good tests requires understanding the architecture well and is a crucial part of the learning experience. Borrowing, copying, consulting, … on the tests is also cheating.

Graduate students (those registered for EE382N.1) will likely be required to do one additional lab.

Useful Links


General Submission Instructions

You will find detailed instructions within each lab assignment. General instructions below.

Labs

Lab 0 (Due 9/7/2017 at 1am | last updated: 8/30/2017)

Lab 1 (Due 9/19/2017 at 1am | last updated: 9/12/2017)

Lab 2 (Due 9/26/2017 at 1am | last updated: 9/19/2017. Assembler is provided now)

Lab 3 (Due 10/10/2017 at 1am | last updated: 9/26/2017)

  • An Example of simulator run
  • The control store template in Excel and PDF formats.

Lab 4 (Due 10/31/2017 at 1am | last updated: 10/10/2017)

  • You can use the following xfig files or pdf files to show the changes you made to the datapath, state diagram and microsequencer. You can modify the xfig files using the xfig drawing program installed on LRC UNIX/Linux machines. Please note that you can submit hand drawn diagrams (You may use the pdf files), if you are not comfortable using xfig.
  • Important note: Make sure your Lab 3 implementation is correct before starting Lab 4. You may use the submit-ee360n command on grader to test your Lab 3 program. Submit the lc3bsim3.c and ucode3 files first with submit-ee360n -late, then run submit-ee360n -lategrade. Run submit-ee360n to see all available options. Passing all the tests does not mean that your Lab 3 is correct! An incorrect program may just happen to behave correctly on our test cases. It is your responsibility to ensure that your Lab 3 is correct. See this for more details.
  • The control store template in Excel and PDF formats.

Lab 5 (Due 11/21/2017 at 1 am | last updated: 10/31/2017)

  • Lab 5 Shell Code
  • Important note: Make sure your Lab 4 implementation is correct before starting Lab 5. You may use the submit-ee360n command on grader to test your Lab 4 program (after slip days). See this for more details.
  • The control store template as a Excel and PDF.
  • You can use the following xfig files or pdf files to show the changes you made to the datapath, state diagram and microsequencer. You can modify the xfig files using the xfig drawing program installed on LRC UNIX/Linux machines. Please note that you can submit hand drawn diagrams (You may use the pdf files), if you are not comfortable using xfig.

Graduate Lab (Due 12/08/2017 at 11:59 pm | last updated: 10/30/2017)

  • This lab assignment is intended for those who registered for the graduate version of this course (EE 382N.1). It accounts for 4% of your total grade.
  • Undergraduate students are welcome to form groups and work on this assignment if you’d like to learn about computer architecture research tools, but you will not receive a grade for this assignment.

Lab 6 (Due 12/8/2017 at 11:59 pm | last updated: 11/21/2017)

  • Lab 6 Shell Code
  • Sample simulator runs to help you in debugging your simulator (Each of the hex files were simulated cycle by cycle using the “run 1″ command and an “idump” was performed after each cycle. *.dump files show the cycle by cycle output of idump. *.state files summarize the contents of the pipeline latches. *.timeline shows a timeline of the execution of the program in the pipeline):

Note that these test cases are not meant to be exhaustive. You should write your own test cases to make sure that your simulator is working for every instruction and program.

  • The new control store template Excel .