In preparation for a talk by David Brooks:
Location: ACES 2.302, Avaya Auditorium
Host: Steve Keckler
Talk Title: “Computer Design in the Nanometer Scale Era: Challenges & Solutions”
Talk Abstract:
Technology scaling has enabled tremendous growth in the computing industry over the past few decades. However, recent trends in power dissipation, reliability, thermal constraints, and device variability threaten to limit the continued benefits of device scaling and curtail performance and energy improvements in future technology generations. The temporal and spatial scales of these effects motivate holistic solutions that span the circuit, architecture, and software layers. In this talk, I will describe several projects that seek to address technology scaling issues. These projects include efforts in the areas of a) power and performance modeling and design space optimization for future chip-multiprocessor systems, b) variability-tolerant microarchitectures that are flexible in both latency and localized supply voltage, and c) accelerator-based architectures for power/performance efficiency. The talk will also discuss our chip prototyping efforts that support this work.
Speaker Bio: David Brooks joined Harvard University in September of 2002 and is an Associate Professor of Computer Science. Dr. Brooks received his B.S. (1997) degree from the University of Southern California and his M.A. (1999) and Ph.D (2001) degrees from Princeton University, all in Electrical Engineering. Prior to joining Harvard University, Dr. Brooks was a Research Staff Member at the IBM T.J. Watson Research Center. Dr. Brooks received an IBM Faculty Partnership Award in 2004, an NSF CAREER award in 2005, and a DARPA Young Faculty Award in 2007. His research interests include architecture and runtime software approaches to address power, reliability, and variability issues for embedded and high-performance computer systems.
