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LectureDateTopic (notes)ReadingComments
11/20Introduction and Policies 
21/22Users and Systems 
31/27GPP binary compatibilityJ. Denhert et al., “The Transmeta Code Morphing™ Software: using speculation, recovery, and adaptive retranslation to address real-life challenges,” CGO’03 
41/29Nanometer designX. Liang et al., “ReVIVaLReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency,” ISCA 2008Comments
52/3GPP source compatibilityS. Swanson et al., “WaveScalar,” MICRO 2003 
62/5GPP source compatibilityS. Swanson et al., “WaveScalar,” MICRO 2003 
72/10GPP virtualizationK. Adams and O. Agesen, “A comparison of software and hardware techniques for x86 virtualization”, ASPLOS-XIIcomments
82/12CMP Resource SharingO. Mutlu and T. Moscibroda, “Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors,” MICRO 2007comments
92/17Defect Tolerance and YieldTWO PAPERS:

1 Y. Zorian and Z. Gizopoulos, “Design for Yield and Reliability”, IEEE Design and Test, Vol. 21, No. 3, May 2004

2 W. Culbertson et al., “Defect Tolerance on the Teramac Custom Computer”, IEEE Symposium on FPGAs for Custom Computing Machines, 1997
 
102/19Reliability and PowerD. Ernst et al., “Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation”, MICRO-36, 2003 
112/24Quiz 1  
122/26Power Reduction IJ. Li et al., “The thrifty barrier: energy-aware synchronization in shared-memory multiprocessors”, HPCA 2004comments
133/3Power Reduction IIC. Isci et al., “An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget,” MICRO 2006 
143/5SimulationJ. Gibson et al., “FLASH vs. (Simulated) FLASH: Closing the Simulation Loop,” ASPLOS 2000 
153/10Compiling for ParallelismA. Lim and M. Lam, “Maximizing Parallelism and Minimizing Synchronization with Affine Transforms”, Symposium on Principles of Programming Languages, January 1997.Hard Paper!
163/12IBM BlueGene/L SupercomupterNicer figures and description but no results: A. Gara et al., “An Overview of the BlueGene/L System Arcyitecture”, IBM Journal of R&D, Vol. 49 No. 2/3, 2005.

K. Davis et al., “A Performance and Scalability Analysis of the BlueGene/L Architecture”, SC’04.
 
173/24Parallel Languages I (Titanium)K. Datta et al., “Titanium Performance and Potential: an NPB Experimental Study”, LCPC 2005.

J. Su and K. Yellick, “Automatic Support for Irregular Computations in a High-Level Language”, IPDPS 2005.
 
183/26HW Active MessagesM. Noakes et al., “The J-Machine Multicomputer: An Architecural Evaluation”, ISCA 20, 1993.

PLEASE ALSO READ THIS OVERVIEW WITH PICTURES: W. J. Dally et al., “The J-Machine: A Retrospective”, 1998.
 
193/31Interconnection NetworksLecture by Prof. Chiouno reading
204/2Lightweight ThreadsD. E. Culler et al., “Fine-Grain Parralelism with Minimal Hardware Support: A Compiler-Controlled Threaded Abstract Machine”,ASPLOS IV, 1991.

BACKGROUND ON ID: K. R. Traub, “A Compiler for the MIT Tagged-Token Dataflow Architecture (pages 13--21 only)”, MIT Masters Thesis, 1986.
 
214/7Stream ProcessorsS. Rixner et al., “A Bandwidth-Efficient Architecture for Media Processing”, MICRO-31 1998.more reading
224/9Supercomputing with StreamsMattan Erez, Online Lecture on Merrimac, 2006

READ: M. Erez et al., “Executing Irregular Applications on Stream Architectures”, ICS’07.
 
234/14Auto-Parallelization for CMPsM. Bridges et al., “Revisiting the Sequential Programming Model for Multi-Core”, MICRO-40, 2007 
244/16Thread-Level SpeculationL. Hammond et al., “Data Speculation Support for Chip Multiprocessors”, ASPLOS-VIII, 1998comments
254/21Generalized StreamingK. Fatahalian et al.,”Programming the Memory Hierarchy”, SC’06 
264/23Reliability TradeoffsM. Erez et al., “Fault Tolerance Techniques for the Merrimac Streaming Supercomputer”, SC’05 
274/28Quiz 2