Please take a look at the scribing instructions and sign up to the scribe list.
Before each class, send me email with answers to these questions. I expect a few bullet points for each answer as preparation for discussion. I don’t want to see long paragraphs!
| Lecture | Date | Topic (notes) | Reading | Comments |
|---|---|---|---|---|
| 1 | 10/14 | Introduction and Policies | notes | |
| 2 | 10/21 | GPP binary compatibility | J. Denhert et al., “The Transmeta Code Morphing™ Software: using speculation, recovery, and adaptive retranslation to address real-life challenges,” CGO’03 | |
| 3 | 10/28 | Reliability and Power | D. Ernst et al., “Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation”, MICRO-36, 2003 A related white paper (I suggest you read it) | |
| 4 | 11/4 | Defect tolerance | O. Temam, “A Defect-Tolerant Accelerator for Emerging High-Performance Applications”, ISCA 2012 Background (no writeup): Y. Zorian and Z. Gizopoulos, “Design for Yield and Reliability”, IEEE Design and Test, Vol. 21, No. 3, May 2004 Great paper I highly recommend and will discuss a little bit even if you don’t read it: W. Culbertson et al., “Defect Tolerance on the Teramac Custom Computer”, IEEE Symposium on FPGAs for Custom Computing Machines, 1997 | |
| 5 | 11/11 | Approximate computing | Discussion paper: H. Esmaeilzadeh et al., “Architecture Support for Disciplined Approximate Programming”, ASPLOS 2012 Another great example: S. Sidiroglou et al., “Managing Performance vs. Accuracy Trade-offs With Loop Perforation”, FSE 2011 Another great example: V. Chippa et al., “Dynamic Effort Scaling: Managing the Quality-Efficiency Tradeoff”, DAC 2011 | |
| 6 | 11/18 | GPGPU | Discussion paper: M. Silberstein et al., “GPUfs: Integrating a File System with GPUs”, ASPLOS 2013 Background: J. Owens et al., “GPU Computing”, Proceedings of the IEEE 96(5), 2008 | |
| 7 | 11/25 | Memory Management | M. Swanson et al., “Increasing TLB reach using superpages backed by shadow memory”, ISCA 1998 Also from wikipedia: some explanation of x86-64 page tables. | |
| 8 | 12/9 | Memory management II | D. Cheriton et al., “HICAMP: architectural support for efficient concurrency-safe shared structured data access”, ASPLOS 2012 | |
| 9 | 12/16 | Memory and ECC | DH Yoon and M. Erez, “Virtualized and Flexible ECC for Main Memory”, ASPLOS 2010 | |
| 10 | 12/23 | Datacenters | Lighter reading: V. Jimenez et al., “Energy-Aware Accounting and Billing in Large-Scale Computing Facilities”, IEEE Micro May/Jun 2011 Research: J. Chang et al., “A Limits Study of Benefits from Nanostore-Based Future Data-Centric System Architectures”, CF 2012 | |
| 11 | Dec-30 | Light-weight Threads | D. E. Culler et al., “Fine-Grain Parralelism with Minimal Hardware Support: A Compiler-Controlled Threaded Abstract Machine”,ASPLOS IV, 1991. BACKGROUND ON ID: K. R. Traub, “A Compiler for the MIT Tagged-Token Dataflow Architecture ‘(pages 13--21 only)’”, MIT Masters Thesis ‘(pages 13-−21 only)’, 1986. Concurrent project about hardware: W. J. Dally et al., “The J-Machine: A Retrospective”, 1998. | |
| 12 | Jan-6 | SW Reliability | S. Chen et al., “Flexible Hardware Acceleration for Instruction-Grain Lifeguards”, IEEE Micro Jan. 2009 | |
| 13 | Jan-13 | Asymmetric Cores | A. Suleman et al., “Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures”, ASPLOS’09 |
