Paper Title: Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation

Problems to solve:

  • Reliable DVFS(DVS) with high efficiency
    • The common DVFS approach was finding the critical delay to adjust clock frequency to optimize supply voltage level.
    • PVT variation(the environments) affects the critical path
    • Process variation is caused by TR doping variation
    • For scaled technology, the controlling of process variation getting difficult
    • DVFS is not a scalable solution at future technology
  • Reliability for varying logic delay
  • The design-guaranteed high voltage margin is unlikely to occur
  • High performance and low energy low cost
  • With decreasing frequency for lower switching power consumption, the static power consumption would increase optimized trade-off point in total power consumption

Users of the system:

  • Everyone can benefit but, design issues, testing, cost would increase

Solution & Uniqueness:

  • Shadow latch + timing speculation
    • Use different phase of clock to guarantee the correctness
    • Verify and correct value at run time
  • Recovery
    • Detect the error → re-do the cycle with the value latched in the shadow latch + margin

Uniqueness:

  • RAZOR’s shadow latch could help shrink the clk aggressively, however, the prior work could not, as they don’t have the recovery mechanism
  • RAZOR needs microarchitecture + CAD support

Metastability:

  • The ability of digital component for a time in a unstable state (unable to settle into either “0” or “1”)

Evaluation:

  • Simulation of Adder
  • uarch simulation:
    • error model
      • if all the path has the same delay, then once we change the voltage, then everything will stop working. This is the opportunity for RAZOR
      • if error vs. volt slope is not sharp, then RAZOR has an opportunity to play the tradeoff
    • uarch model
    • Use both “random” + “benchmarks” to evaluate
  • FPGA Emulation Multiplier
  • Prototype on Alpha with RAZOR
    • Prototype is a single instance, some uncertainties could exist
    • good for evaluating the cost
  • Measure:
    • efficiency, IPC; RAZOR used the fixed frequency + var volts in the experiments (fixed frequency may lead to lose potential saving opportunities)
    • metric: (INST/J)
    • cost:
      • RAZOR latch
      • Voltage regulator
      • Logic
      • min path constraint, so needs additional buffers
  • How to choose baseline in the evaluation:
    • state-of-the-art work
    • worst case

Three Categories for power margin reduction: 

 * Monitor
 * RAZOR
 * Canary circuit

Other factors that could change the margin: 

 * Aging
 * Temperature
 * Voltage noise, droops, supply voltage
 * process variations