Paper Title: Quality Programmable Vector Processors for Approximate Computing

Problem :

  • Approximate computing
    • Tradeoff quality for energy
      • Quality metrics: average error, max error, SNR(normalized mean squared error)
    • Modern computers have some approximate computing concepts already
      • Multiple integer data types
        • Overflow is a problem
        • Saturation computation is utilized instead
      • Floating point representation for real numbers
        • Float v.s. double
      • Fixed point (popular in embedded systems)
        • How to determine the optimal bits for fraction part?
        • How to perform conversion between floating and fixed point without losing much precision?
    • Target applications: Resilient applications
      • Inexact outputs are acceptable (end users are usually human beings)
      • e.g. signal processing, machine learning, etc.
      • Counter example: banking applications

Users of the system:

  • Resilient application programmers/users
    • Quality control at application level
  • Compiler programmers
    • Optimization for energy
  • Architects
    • Microarch to implement the specified ISA

Uniqueness in solution:

  • Enabling configurable quality in ISA
    • Previous works only tagged if instructions can be approximated or not
  • Exploring approximate computing in the context of vector processors
    • Why vector processors?
      • ALUs lead to major energy consumption
      • Target applications use many vectorizable computation (e.g. matrix multiplication)
    • Why not general-purpose cores?
      • Control and decoding are power-hungry compared with execution units

Mechanisms for saving energy:

  • Three types of ALUs
  • Bit Truncation of ALU operands (Precision Scaling)
    • How come energy is saved?
      • Less switching on transistors in ALUs
    • Make critical path shorter (shorter carry chain)
      • Provide opportunity for DVFS
  • How to deal with leakage?
    • Clock gating of pipeline registers for truncated inputs
    • Power gating (not covered in the paper)
      • Cost: additional tailored transistors
    • Voltage scaling
      • Pro: quadratic reduction in power
      • Con: timing slack

Evaluation:

  • RTL implementation for single-instruction energy consumption
  • Simulation for dynamic instruction counts to compute total energy
    • What is the problem of calculating energy this way?
      • Missing pipeline effect
  • Sensitivity Analysis
    • Precision scaling mechanisms
    • Array dimensions
  • What can we learn from evaluation?
    • Experimental results verify motivation
      • Fig. 1 shows ratio of approximate instructions, while Fig. 15 shows energy reduction
    • Missing components in the evaluation
      • No baseline
      • No performance evaluation
      • DVFS is not addressed
      • Missing data in Figure. 14
        • Reviewers should have asked authors to fix it

Technology’s role:

  • As devices scale down, leakage becomes an issue
    • This work focuses on dynamic power instead of leakage
    • They can provide leakage for 45nm process to show that static power is less significant compared with dynamic power

Generalization for the class:

  • Hardware raises quality control to software level by providing interfaces in ISA
  • System cost can be reduced by tailoring results to meet users’ requirements