DrSim is a cycle-based DRAM system simulator, like DRAMSim.

Our goal in writing a new DRAM simulator was flexibility, to easily experiment with a variety of DRAM system topologies, including sub-ranked systems. Current DrSim release is for memory systems research, and not trying to provide an out-of-box DRAM simulator experience.

Min Kyu Jeong, Doe Hyun Yoon, and Mattan Erez. DrSim: A Platform for Flexible DRAM System Research. \urlhttp://lph.ece.utexas.edu/public/DrSim. (BibTeX)

    title = {DrSim: A Platform for Flexible {DRAM} System Research},
    author = {Min Kyu Jeong and Doe Hyun Yoon and Mattan Erez},
    howpublished = {\url{http://lph.ece.utexas.edu/public/DrSim}}}


DrSim source


DrSim traces


Building DrSim

DrSim is built using standard Make and g++. Two files are generated: A trace-driven simulator executable (drsim) and a shared object (libdrsim.so) to be linked with processor simulators.

 $ make

builds an optimized version (-O3) without logging/tracing (fastest).

 $ make dbg=1

builds a debug version (-g) with logging/tracing.

 $ make opt=1

builds an optimized version (-O3) with logging/tracing.

Using DrSim

DrSim is a set of C++ classes that models the DRAM memory subsystems components. A user instantiates the modules with parameters and connects the objects to model the memory system.

Then, a memory master (either a trace-reading frontend or a processor simulator) clocks the system and sends memory requests. When a request is finished, a call-back function for the request is called to let the user handle the response.

You can take a look at the provided memory master examples to see how the modules are set up.

Trace-driven frontend (frontend/drsim_trace_main.cpp)

A trace-driven frontend is an example of a memory master. It reads a memory trace and sends the requests to the memory system.

Gem5 glue

Gem5 interface code can be found in gem5_glue directory. The following steps illustrate the integration of DrSim with Gem5, as a dynamic library.

Gem5 version used in this example was changeset: 8902:75b524b64c28 (tip as of 3/21/2012). Note that old version of Gem5 has different PhysicalMemory definition which is not compatible with this glue. The related changeset is documented at http://repo.gem5.org/gem5?cmd=changeset;node=c7e14f52c682

Assuming $GEM5PATH and $DRSIMPATH point to the Gem5 and DrSim base path in which DrSim has been built already.

1. Make a directory for DrSim glue in Gem5 source tree.

 $ mkdir $GEM5PATH/src/mem/drsim

2. Copy the glue code.

 $ cd $DRSIMPATH/gem5_glue
 $ cp drsim.cc drsim.hh Drsim.py SConscript SConsopts $GEM5PATH/src/mem/drsim

3. Copy the DrSim header files.

 $ cp -r inc $GEM5PATH/src/mem/drsim/drsiminc

Note: I used to use symbolic links to the header directory. However, the boost header-only library DrSim uses is incompatible with SCons (has implicit dependency not detectable with SCons http://www.scons.org/doc/2.1.0/HTML/scons-user/x1239.html), and a workaround requires actual copying of the header files.

4. Build

 $ scons DRSIM_LIB_PATH=$DRSIMPATH/obj-release

Build would fail with the following error message.

 build/ALPHA/mem/drsim/drsiminc/boost/config.hpp:26:29: fatal error: boost/config/user.hpp: No such file or directory

Workaround: manually copy the drsiminc directory files to the build directory.

 $ cp -r src/mem/drsim/drsiminc build/ALPHA/mem/drsim/

Try again and it should generate build/ALPHA/gem5.debug binary.

5. Instantiate DrSim SimObject in your Gem5 configuration script.

In place of the memory previously used (ex. PhysicalMemory), instantiate DrSim. For example, the following change is made to configs/example/se.py confiuration script.

 169 system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
 170                 #physmem = PhysicalMemory(range=AddrRange(“512MB”)),
 171                 physmem = DrSim(range=AddrRange(“512MB”)),          
 172                 membus = Bus(), mem_mode = test_mem_mode)

In this glue code, drsim_config string parameter (in DrSim.py) is used to pass DrSim parameters. For example, the following configuration script instantiates 2-channel, 2-rank system.

 169 system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
 170                 physmem = DrSim(range=AddrRange(“512MB”),
 171                                 drsim_config=“--channel:2:--rank:2″),
 172                 membus = Bus(), mem_mode = test_mem_mode)

6. Add DrSim directory to the library search path.

 $ export LD_LIBRARY_PATH=$DRSIMPATH/obj-release

7. Run

Run it with a timing memory model (timing or O3).

 $ build/ALPHA/gem5.debug configs/example/se_drsim.py —cpu-type=timing
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled Mar 22 2012 21:41:39
gem5 started Mar 22 2012 21:48:20
gem5 executing on hopper
command line: build/ALPHA/gem5.debug configs/example/se_drsim.py --cpu-type=timing
Global frequency set at 1000000000000 ticks per second
*** drsim args ***
[System Configuration]
DRAM Clock Freq (CK, MHz)      : 800
Number of DRAM channels        : 2

[Channel Configuration]
Number of Ranks per channel    : 2
Number of Chips per rank       : 8
Number of ABUS per channel     : 1

[Chip Configuration]
Number of Banks per chip       : 8
Number of Rows per bank        : 32768
Number of Columns per row      : 1024
Chip width in Bytes            : 1
Burst length                   : 8

[Scheduler Configuration]
Read Queue Size                : 64
Write Queue Size               : 64
Scheduler                      : FR_FCFS
Closed Page                    : 0
WMode Allow READ CAS           : 0
RMode Allow WRITE ACT/PRE      : 0
WMode Enter Threshold          : 48
WMode Exit Threshold           : 16
Starvation Threshold           : 1000
Powerdown                      : 0
per_req_policy:                : 0
split:                         : 0
cw_priority:                   : 0
use_repeat_queue:              : 0
rot_q_search_off:              : 0
multi_cas:                     : 0
highp8:                        : 0
split_cwf:                     : 0

[Decoder Configuration]
bank_interleave:               : 0
rank_interleave:               : 1
subrank width :                : 8
bank xor_hash:                 : 1
subrank xor_hash:              : 1
channel xor_hash:              : 0

[DRAM timing configuration]
Data Clock Rate: 2
ABus additional delay: 0
Burst: 	4 in A Bus clock, 	8 in D Bus clock
AL: 	0	CAS: 	10	CCD: 	4	CMD: 	1	CWD: 	8
FAW: 	24	OST: 	0	RAS: 	28	RC: 	38	RCD: 	10
RFC: 	88	RP: 	10	RRD: 	5	RTP: 	6	RTRS: 	2
WR: 	12	WTR: 	6	REFI: 	6240

[Address Decoding Map]
decoder id: 0
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
info: Entering event queue @ 0.  Starting simulation...
info: Increasing stack size by one page.
Hello world!
hack: be nice to actually delete the event here
Exiting @ tick 164834000 because target called exit()

Reminder and random tips.

You are responsible for using realistic DRAM parameters. Current DrSim release is not intended to be an out-of-box DRAM simulator. Although we didn’t intentionally put in unrealistic default parameters, you should understand what you are simulating.

  1. Hashing offsets ({bank,subrank,channel}_xor_hashing_offset) should be set correctly if you turn XOR hashing on. For example, in the prev. example, bank hashing index is in bit 31. You probably don’t want that. It happened because the llc_tag_shift was not set properly (see the comment in drsim.cc)
  2. Default values of policy parameters (ex. age_promo_threshold, wm_enter/exit) are not tuned. We are not claiming they are good values.
  3. Some experimental knobs are left in. Play with them at your own risk :)
  4. Library names are different (libdrsim.so, libdrsimdbg.so, libdrsimopt.so) base on the version. This was to link with matching versions of processor simulator binary (Gem5 dbg, opt, fast).